The present invention relates to D-type flip-flop circuits and specifically to a D-type flip flop circuit (referred to as D-F/F, hereinafter) in which, when there is a failure in D-F/F, the failure sets the flip-flop to a predetermined logic state.
A D-type flip flop is a flip-flop whose output is a function of the input which appears one clock pulse earlier; for example, if a binary "1" appears at the input, the output after the next clock pulse will be a "1".
FIG. 1 shows an example of conventional D-F/F. In this Figure, symbols Q1, Q2, Q3 and Q4 represent NAND gates. The inputs to NAND gate Q1 are an input signal from terminal A and a clock signal on terminal B. NAND gate Q2 receives as inputs the output from the NAND gate Q1 and the clock signal.
The NAND gates Q3 and Q4 are cross connected to constitute a non-synchronous flip-flop circuit which receive, as its set input signal and its reset input signal, the outputs from the first and second NAND gates Q1 and Q2, respectively. The output from the D-F/F on terminal D can be set to an initial value (binary "1" or binary "0") by an initial set signal applied to terminal C.
The operation of this prior art D-F/F will be understood from the timing chart shown in FIG. 2A. The flip-flop is set initially by a signal on terminal C. Thereafter the D-F/F is set and reset by a combination of the input signal applied to terminal A and the clock input signal, so that an output signal as shown by waveform "output of F/F CKT" in FIG. 2A follows the input shifted by one clock pulse.
A problem with this prior art D-F/F arises if the output of the NAND gate Q1 is not applied to the NAND gate Q4 due to a failure, such for example as a burning out of the wire. In this case the D-F/F operates in the manner shown in FIG. 2B.
Namely, after the input signal changes from "1" to "0", the output signal changes from "1" to 37 0" and remains in this state.
According to the invention, in the event that the output signal is not obtained as the signal shifted from the input signal, the output is changed without fail from "1" to "0" before the input is changed to "0" and this state is maintained, thereby to find out beforehand that the apparatus is not functioning as a shift register, thereby to prevent the apparatus (not shown) using this D-F/F from operating erroneously.